FPGA on DE0-Nano accessing the EPCS64

I believe I wrote that comment because for some lame reason Quartus won't let you synthesize a design if you have "Active Serial" mode selected as the configuration mode and your design has logic that accesses the EPCS pins. So that comment applies to the Quartus setting, rather than the actual hardware level implementation. Of course, my recollection might be wrong, in that it might be PS mode that is the problem (since in PS mode, DCLK becomes fixed as an input).