New ContributorFitter doesn't assign HPS DDR3 pins
Hi,
Im using the DE10 Nano SystemBuilder to create a projet.
I add the Cyclone V HPS in Platform Designer with the right SDRAM parameters (I tried with presets and from the datasheet) and generate.
I update my top module to connect the SOC System to the clock and memory pins.
I then add the .qip to my projet run Analysis & Synthesis and execute the pin_assignments tcl.
When I run the Fitter I get the error "Error (179000): Design requires 193 user-specified I/O pins -- too many to fit in the 145 user I/O pin locations available in the selected device" as if the memory pins were assigned to the user GPIO.
Any ideas where my mistake is (my projet is in attachment) ?
First thing is that you had look into the wrong table, you should look into the table 11 U670 device, which only have 145 IO
second is that you have HPS inout pin that is not connected to the module, Quartus will not able to identify those pin are HPS thus it will assume it as the GPIO. This will cause it have more GPIO pin.
// inout HPS_I2C0_SCLK,
// inout HPS_I2C0_SDAT,
// inout HPS_I2C1_SCLK,
// inout HPS_I2C1_SDAT,
// inout HPS_KEY,
// inout HPS_LED,
// inout HPS_LTC_GPIO,
// output HPS_SD_CLK,
// inout HPS_SD_CMD,
// inout [3:0] HPS_SD_DATA,
// output HPS_SPIM_CLK,
// input HPS_SPIM_MISO,
// output HPS_SPIM_MOSI,
// inout HPS_SPIM_SS,
