Forum Discussion
New ContributorFitter doesn't assign HPS DDR3 pins
First thing is that you had look into the wrong table, you should look into the table 11 U670 device, which only have 145 IO
second is that you have HPS inout pin that is not connected to the module, Quartus will not able to identify those pin are HPS thus it will assume it as the GPIO. This will cause it have more GPIO pin.
// inout HPS_I2C0_SCLK,
// inout HPS_I2C0_SDAT,
// inout HPS_I2C1_SCLK,
// inout HPS_I2C1_SDAT,
// inout HPS_KEY,
// inout HPS_LED,
// inout HPS_LTC_GPIO,
// output HPS_SD_CLK,
// inout HPS_SD_CMD,
// inout [3:0] HPS_SD_DATA,
// output HPS_SPIM_CLK,
// input HPS_SPIM_MISO,
// output HPS_SPIM_MOSI,
// inout HPS_SPIM_SS,
Super ContributorThose fitter location are automatically generated with the Top level design port that you have declared in the verilog code. If you see clearly, you have about 190++ pin declared, and out of it, the GPIO pin is not totally used:
//////////// GPIO_0, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_0,
//////////// GPIO_1, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_1
You only used it with
.uart0_rxd (GPIO_0[0]),
.uart0_txd (GPIO_0[1])
If you are not using so much, can you reduce it in your top level?
fcabIn the Cyclone V Device Overview at page 13 you can see that my device has 288 FPGA GPIO and 181 HPS I/O.
In my design FPGA GPIO = ADC (4) + ARDUINO (17) + HDMI (35) + KEY (2) + LED (8) + SW (4) + GPIO_0 (36) + GPIO_1 (36) = 142 < 288 and HPS I/O = HPS* (120) = 120 < 181 in either case Im well below the limit.
