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Altera_Forum
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9 years ago

FFT in DE0 Nano board

Hi,

i have recently bough DE0 nano board and i am beginner in Verilog. I went through the ADC code given in CD and i am comfortable in understanding how the external data is captured using the ADC via SPI interface.

Holistically, i want to capture 8 signals at a sampling frequency of 20-50 kHz and take FFT on them. From the FFT vaues of different signal, i would like to get the information of odd harmonics component by using a for loop and send the final value via SCI to a micro-controller. As the total number of samples are much higher 8*50000, the data points have to be saved in external SDRAM. With my current knowledge i could capture the data and save it in a variable.

I would be really grateful if i get the guidance and opinions from the experts.

Regards,

subash

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Depends on how many points you need for the FFT. The more points you buffer, the better your frequency resolution will be but you will require much more memory. Suppose you use a 4096 point buffer then you will have 50000/4096 = 12.2Hz resolution. But you also need to consider the bit size of your values. So if you have 8bit values, 8 channels, and 4096 point /channel then you will need 32kB of RAM to hold these data points. Unfortunately, this is still way before all the calculations that occur in a DFT. Please review this paper: https://www.researchgate.net/publication/235995761_the_fast_fourier_transform_in_hardware_a_tutorial_based_on_an_fpga_implementation

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi Kranser,

    Thanks for sharing the document. It was really helpful in understanding the computational procedure for FFT in FPGA. In that research article FFT is implemented using discrete blocks.

    But i would like to use the FFT block given in IP core library. The on chip RAM for cycle IV is small, hence i have to use the external RAM of 32 MB provided in the DE0 nano kit. I looked the FFT block given in the FFT megacore. I went through the IP core documentation for FFT and could understand the purpose of each pin available in the FFT megacore. However, to clearly understand the FFT mega core block, an example project is required .It would be really helpful if there is any FPGA project for FFT in DE0 nano using the external SRAM. Would you be able to provide such a project file, so that i could understand and clarify my doubts ?

    Regards,

    subash