Forum Discussion
Fast & Large block data transfer over USB - DE1/DE2 ?
Hi I have a DE1 fpga module, which has a single USB port that seems to be dedicated to programming. Is it possible to use it to do fast, large block data transfers over the USB ?
I see quite a bit of discussion here in a similar vein, but do not see anything conclusive. I see the USB is connected to an FTDI FT245BL - this should be capable of 1M Byte / Sec, using their D2XX Drivers. It is then connected to an Altera MAX chip. Previous fpga modules that I have used with FTDI chips have been able to use the USB port for both programming and for data transfer. Or am I better to junk the DE1 board and buy a DE2 which I see has a second USB port ? cheers, Beau54 Replies
- Altera_Forum
Honored Contributor
You could try using the JTAG Avalon Master component and driving it from SystemConsole. This gets transfer rates pretty close to the maximum raw JTAG rate (the latter is about 5Mb/s write only on Linux for large transfers, windows is I think about 3Mb/s. I don't have the exact figure for the Avalon write bandwidth on me I'm afraid).
- Altera_Forum
Honored Contributor
--- Quote Start --- I tried both the latest version of VMWare (workstation 7.1) and VirtualBox, and neither could capture the USB-Blaster to sniff from Linux in a VM. I installed Ubuntu 11.04 (Wubi - binary blob on the windows partition), and it works great. --- Quote End --- I stopped to update my copy of Cygwin, and so a web search, but could not see a version of Wireshark I could just try under Cygwin. --- Quote Start --- Apart from being able to access the USB Blaster through ftd2xx.dll, how do you want connect to the FPGA on the DE1/DE2 side? Did you notice, that DE1 and DE2 implement a second set of software JTAG lines between the embedded USB-Blaster CPLD and the FPGA? The interface is used in the DEx_USB_API demonstration for data transfer from and to the Control Panel application. Alternatively, you have communication options based on the VJTAG channel, e.g. the JTAG UART. --- Quote End --- This is where I am fairly ignorant - I have as yet never made use of JTAG or VJTAG .... I have been using an "8-bit port into block of registers" with a simple 4-byte address and read/write data protocol, via the FTDI chips, partly inherited from an early set of fpga modules, and partly extended by myself .... been using it for a number of years, for a range of fpga projects. I am trying to port this to the Morphic II - frustratingly is seems to sometimes work but mostly not, so I expect the state machine breaks when run faster. If we can build a bi-directional byte-stream vie the usb blaster to the FPGA, this could work on the DE1 as well ? This would be the first part of the project. The second would be to write a "block" transfer mode, to read the contents of a large block of memory. At this point I really need advice on how to build a 4 byte-stream interface from the PC to the DE1, ideally as fast as possible. Then I can immediately run quite a bit of code. Writing is : Write 4 bytes Reading is : Write 3 bytes (or 4), Read 1 byte. Not very efficient, but very flexible. - Altera_Forum
Honored Contributor
--- Quote Start --- You could try using the JTAG Avalon Master component and driving it from SystemConsole. --- Quote End --- Thanks - I am chasing up on JTAG, and on Avalon (which I have used). The computer end I want to be my own programs (written in Apl). AplX from MicroApl talks to the FTDI DLL fine, I use it to control my NMR spectrometer, which has a number of FTDI interfaced fpgas built into it now. It was AplX I used for those quick tests on the USB Blaster, a few pages ago. - Altera_Forum
Honored Contributor
I'm writing some detailed documents along with example code for;
* custom VJTAG components * FTDI FIFO-to-Avalon-MM bridges * customized use of the USB-Blaster, eg. for VJTAG communications Be patient, and I'll post links soon. At the moment I'm writing TimeQuest analysis scripts for the designs. Cheers, Dave - Altera_Forum
Honored Contributor
--- Quote Start --- I'm writing some detailed documents along with example code for; * custom VJTAG components * FTDI FIFO-to-Avalon-MM bridges * customized use of the USB-Blaster, eg. for VJTAG communications Be patient, and I'll post links soon. At the moment I'm writing TimeQuest analysis scripts for the designs. Cheers, Dave --- Quote End --- WoW ! Thanks ! - Altera_Forum
Honored Contributor
--- Quote Start --- Great. I haven't tried accessing a USB-Blaster under windows. Write some test code; a) Toggle TCK, while keeping all other bits high, so according to the protocol: 0011_1111 b /* bit mode, don't read-back, OE + TDI + CS# + CE# + TCK high */ 0011_1110 b /* drop TCK low */ So fill a write buffer with 3-bytes, i.e., 3Fh, 3Eh, 3Fh, and write it to the USB-Blaster. Probe the TCK pin and you will see a ~1us low pulse on TCK. Viola, you now have control of your USB-Blaster! Cheers, Dave --- Quote End --- Well yes and no ..... I have for a USB Blaster JTAG connector connected to the JTAG connectore on Morphic II, being the easiest for me to test : Orientation : Pins 2, 10 : Gnd Pin 4 : Vcc Then the JTAG connectors are bought out to Morhic IO connectors : Morphic II 0.1" connectors Altera USB Blaster (JTAG Mode) J3-23 JTAG_TDI JTAG Interface Pin 9 J3-24 JTAG_TMS JTAG Interface Pin 5 J4-23 JTAG_TDO JTAG Interface Pin 3 J4-24 JTAG_TCK JTAG Interface Pin 1 If Toggle Toggling Bit 0 TDI Pin 9, TMS Pin 5 If I write the 3Fh, 3Eh, 3Fh to the USB Blaster (and then call a Tx purge) Or as decimal and binary : 63 62 63 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 Then I have toggling : TDI Pin 9, TMS Pin 5, with TCK and TDO low. This is indeed a 1us low pulse. In fact it does not seem to matter which bit I toggle (other than the far left one), I get the same behaviour. Puzzled. - Altera_Forum
Honored Contributor
Perhaps you did not reset the JTAG TAP machine before starting your test.
Take a look at this test code. Cheers, Dave - Altera_Forum
Honored Contributor
Ah, thanks indeed, I will read it and try again tomorrow.
cheers, Beau - Altera_Forum
Honored Contributor
Well I had a quick go ....
The reset string is : jtag_reset 63 62 63 62 63 62 63 62 63 62 63 129 255 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Yes ? I really wonder if this is suffering from the same problem as I am having with the Morphic II driving software. - Altera_Forum
Honored Contributor
Lets see ...
--- Quote Start --- The reset string is : 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 --- Quote End --- This is the bit-mode TAP reset sequence; it starts but putting all JTAG signals high, and then toggles TCK 5 times. --- Quote Start --- 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 --- Quote End --- This is the 'alternative' method using byte-mode commands. The commands are; send a byte-mode command with 1-byte, followed by a byte of all 1's. This will toggle TCK 8 times. However, prior to this you need to set all the bits high, i.e., the correct sequence if using byte-mode is --- Quote Start --- 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 --- Quote End --- Cheers, Dave