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CAlex's avatar
CAlex
Icon for Contributor rankContributor
1 year ago

F2SDRAM : mSGDMA endian issue and SDRAM reading/writing issue

Hi I'm working on CycloneVsoc Dev Kit baremetal system Now I want to use F2H sdram to transmit my data. The draft system Interconnection: HPS host master | | host order | SelfIP...
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Fpga Devkit
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi CAlex,


I will close the thread if no further question.


Thanks.

Regards,

Aik Eu