Well, this is my VHDL code :
---------------------- Frequency division by 2 -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------
ENTITY freq_div2 IS
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
out2 : OUT STD_LOGIC);
END freq_div2;
-----------------------------------------
ARCHITECTURE example OF freq_div2 IS
signal clk_div : std_logic :='0';
BEGIN
process (clk, reset_n, clk_div)
variable countr : integer range 0 to 7:= 0;
begin
if reset_n ='0' then
countr :=0;
elsif (clk'event AND clk = '0') then
countr := countr +1;
if countr =1 then
clk_div <= not clk_div;
countr :=0 ;
end if;
end if;
end process;
out2 <= clk_div;
end example;
Then I use the (Pin Planner) to assign the (clk) to the appropriate clock pin. For example (PIN_N2) for (50 MHz). How do you suggest I use the (PLL)?? Thanks a lot.