Ethernet with NiosII on Cyclone III FPGA Board?

AFAIK the example design for the embedded kit uses the Ethernet interface from the daughter board so it won't work on the Cyclone III development kit alone.

What error do you have when you try to open the first project? It should work.

The example of Tse (altera\81\kits\cycloneIII_3c120_embedded\examples\standard) is working only on Quartus II above 8.0 version.

It works on 8.1 but failed on 8.0.

Now i try understand where can i find the pinouts(from shematic maybe)?

And i have a question - if i try 100 mbps i should use 25Mhz clock on rx and tx clocks? Where about the pins ena_10 and eth_mode, how and where should i connect them?

Ok.

But i can't understand how to pin tx and rx?

from manual on cyclone III:

25 MHz (reference clock); enet_rx_clk Input U5 Cyclone III device pin B14

ENET_GTX_CLK T8 - Clock Outputs

So how can I pin the enet_rx_clk Input Clock B14 if it generates 25Mhz clock

i can't understand it.

Connect ENET_RX_CLK to rx_clk_to_the_tse_mac

Connect a local 25MHz clock source to both ENET_GTX_CLK (wich is an output, not an input) and tx_clk_to_the_tse_mac

Unfortunally there is no information about the direction of these signals in manual for CIII:

ENET_RX_D[3..0]

ENET_TX_D[3..0]

ENET_TX_EN

ENET_RX_DV

How or where can i find them?

I suppose that outputs are:

ENET_TX_D[3..0]

ENET_TX_EN

and inputs:

ENET_RX_DV

ENET_RX_D[3..0]

A'm I right?

What do you mean? They are documented on both the board reference manual and the TSE datasheet.

You supposed right.

This is the example of pin description in the cyclone III manual:

U5 pin 2 RGMII interface receive clock 1.8 V ENET_RX_CLK B14

U5 pin 95 RGMII interface receive data bus bit 0 2.5 V ENET_RX_D0 W8

U5 pin 92 RGMII interface receive data bus bit 1 2.5 V ENET_RX_D1 AA6

U5 pin 93 RGMII interface receive data bus bit 2 2.5 V ENET_RX_D2 W7

and for examplу of flash description:

Signal Name Description I/O Standard

FSM_A(24:0) Address bus (word aligned) 1.8-V LVCMOS out (25 bits)

FSM_D(15:0) Data bus N/A (Accounted for in SRAM section)

FLASH_CSn Chip select 1.8-V LVCMOS out

FLASH_OEn Output enable 1.8-V LVCMOS out

FLASH_WEn Write enable 1.8-V LVCMOS out

FLASH_RSTn Reset 1.8-V LVCMOS out

here we can find if it is out or in.

receive = input

for the flash everything is an output except the data bus that is bidirectional.

Hello Dai -

Wondering if you were able to locate your Gig-E design? The design on the nioswiki has so much extra added to it (due to using the standardized linux platform w/ 2 nios devices, lcd, etc) that it is not a useful jumping off point for people who need as much free fpga space as possible...

-Chris

There is no design example available and I think there will never be. You can't use the CII example because it uses a different chip. Altera really screwed up on the CIII kit, less than half the board is actually usable straight out of the box.

I made a design a while ago on that kit with an Ethernet connection, but it had some restrictions (Gigabit only, need to modify the ipport.h file, etc...). I posted it a while ago on the Nios forum but can't find it now. I'll see if I can find it again.

last edited by daixiwen : september 25th, 2009 at 01:40 am.

http://www.alteraforum.com/forum//proweb/buttons/quote.gif (http://alteraforums.net/forum/newreply.php?do=newreply&p=73089)