Ethernet with NiosII on Cyclone III FPGA Board?

This is the example of pin description in the cyclone III manual:

U5 pin 2 RGMII interface receive clock 1.8 V ENET_RX_CLK B14

U5 pin 95 RGMII interface receive data bus bit 0 2.5 V ENET_RX_D0 W8

U5 pin 92 RGMII interface receive data bus bit 1 2.5 V ENET_RX_D1 AA6

U5 pin 93 RGMII interface receive data bus bit 2 2.5 V ENET_RX_D2 W7

and for examplу of flash description:

Signal Name Description I/O Standard

FSM_A(24:0) Address bus (word aligned) 1.8-V LVCMOS out (25 bits)

FSM_D(15:0) Data bus N/A (Accounted for in SRAM section)

FLASH_CSn Chip select 1.8-V LVCMOS out

FLASH_OEn Output enable 1.8-V LVCMOS out

FLASH_WEn Write enable 1.8-V LVCMOS out

FLASH_RSTn Reset 1.8-V LVCMOS out

here we can find if it is out or in.