Ethernet with DSP Dev. Kit Cyclone III (no NIOS)

I didn't ;)

When you start to put a Nios processor and a TSE to a system, the compile time increases a lot.

Well, so far I can create the NiosII3C120DesignExample.

But if the board is OK I wonder why my Triple Speed Ethernet Core in Quartus does not work... Do you have a simple fpga design with TSE that works or do you have only NIOS software?

I had a simple design on the Nios forum, but not as good as thi one from the wiki. It would work only in gigabit mode.

But if on your design the PHY doesn't even autonegotiate a speed, the problem must be a simple one, related to signals directly connected to the PHY. Maybe the reset signal, a clock, or one of the MDIO signals. You can try and find the differences between your design and the wiki example in those areas.

Finally at least the physical connection works with the FPGA. :)

I think I owe you to say where the error was:

I connected resetN to an (unassigned) input with default value = VCC. This was obviously wrong. I deleted the input pin and replaced it with primitives > other > vcc and then it worked.

I was about to suggest to put a proper reset signal generator for the PHY. The Nios example uses one (in global_reset_generator.v) that could serve that purpose.

The marvel chip is known for having reset issues on the Stratix board (it won't init properly if it didn't have a reset pulse at power up) but as far as I know the Cyclone III board doesn't have the problem. Still it is a good idea to reset properly the PHY at power up, it can't hurt ;)

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Still it is a good idea to reset properly the PHY at power up, it can't hurt ;)

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Yes, I noticed too that it sometimes doesn't work if no reset is done at startup.

To send packets I think that I must prepare three things:

• clock setup

• time constraints

• register settings

For clock setup I have:

ff_tx_clk = ff_rx_clk = 25 MHz

clk = 125 MHz

tx_clk = 125 MHz

enet_gtx_clk = 125 MHz + 90°

For Time constraints I use the skript tse_constraints.tcl and Classic Timing Analyzer. (But I still get Critical Warnings).

Register settings I do like following:

I want to set TX_ENA (bit 0) and RX_ENA (bit 1) in Command_Config Register which is at Address Offset 0x008, so I do:

data <= "00000000000000000000000000000011"; -- (32 Bit)

addr <= "00001000"; -- 0x008

write <= '0'; -- this makes a falling edge of write

I think that's not 100% right so maybe you can tell me where I misunderstood something...?

From where do you get information except of the TSE User Guide?

I suggest reading the avalon specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf).

The write signal is normally '0'. To perform a write, supply the correct vectors to writedata and address, change write to '1', wait until waitrequest is '0', and change write to '0' again (except if you want to write again)

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...wait until waitrequest is '0'...

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Somehow waitrequest is always 1. I have put read and write to GND but still waitrequest is 1. Maybe it is inverted, but then it would be named waitrequest_n. The register clock (clk) is 25 MHz which I think is OK.

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Did you reset the TSE core before using it?

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Yes, I resetted TSE as well as the PHY.