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Still it is a good idea to reset properly the PHY at power up, it can't hurt ;)
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Yes, I noticed too that it sometimes doesn't work if no reset is done at startup.
To send packets I think that I must prepare three things:
- clock setup
- time constraints
- register settings
For clock setup I have:
ff_tx_clk = ff_rx_clk = 25 MHz
clk = 125 MHz
tx_clk = 125 MHz
enet_gtx_clk = 125 MHz + 90°
For Time constraints I use the skript
tse_constraints.tcl and Classic Timing Analyzer. (But I still get Critical Warnings).
Register settings I do like following:
I want to set TX_ENA (bit 0) and RX_ENA (bit 1) in Command_Config Register which is at Address Offset 0x008, so I do:
data <= "00000000000000000000000000000011"; -- (32 Bit)
addr <= "00001000"; -- 0x008
write <= '0'; -- this makes a falling edge of write
I think that's not 100% right so maybe you can tell me where I misunderstood something...?
From where do you get information except of the TSE User Guide?
Honored Contributor
