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VSA00's avatar
VSA00
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6 years ago

Error in Signal Tap Logic Analyzer

Hi,

I am trying to read a continuous clock signal (125MHz) via IO pin (Bank 8A ,Pin no: L8 ,Pin Name: IO_8A_L8/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T57P)

on my custom made cyclone v fpga board.

FPGA : Cyclone V 5cgxfc9d6

Debugger : USB Blaster Rev C

But when viewed through signal tap what i have observed is as shown below.

The signal is not continuous.

In order to figure out the issue i tapped the incoming signal with DSO , it is continuous. But in signal tap logic analyzer it is not continuous.

Used Internal PLL for generating 300Mhz clock for sampling the signal.

Why this happens.

Kindly help me to resolve the issue.

Regards,

Vijesh

5 Replies

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi Vijesh,

    From the signal tap, I felt like the sampling clock frequency is same or low.

    As part of debugging, make one PLL and try to take the out put see pll out put is coming corrctely or not and lock signal is been high.

    The above proves that the clock signal is good

    • VSA00's avatar
      VSA00
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi @RahulS_Intel​ ,

      Verified the generated PLL output (300MHz) through DSO. Its coming correctly.

      Thanks.

      Regards,

      Vijesh S A

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Now also the signal tap analyser is showing the discontinuity -- This may be due to the board issue. may be signal integrity issue .