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VSA00's avatar
VSA00
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6 years ago

Error in Signal Tap Logic Analyzer

Hi, I am trying to read a continuous clock signal (125MHz) via IO pin (Bank 8A ,Pin no: L8 ,Pin Name: IO_8A_L8/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T57P) on my custom made cyclone v fpga board. FPGA : Cyc...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
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6 years ago

Hi Vijesh,

From the signal tap, I felt like the sampling clock frequency is same or low.

As part of debugging, make one PLL and try to take the out put see pll out put is coming corrctely or not and lock signal is been high.

The above proves that the clock signal is good

  • VSA00's avatar
    VSA00
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    6 years ago

    Hi @RahulS_Intel​ ,

    Verified the generated PLL output (300MHz) through DSO. Its coming correctly.

    Thanks.

    Regards,

    Vijesh S A

    • Rahul_S_Intel1's avatar
      Rahul_S_Intel1
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      6 years ago

      Glad to know

    • VSA00's avatar
      VSA00
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      6 years ago

      Hi @RSree (Intel)​ ,

      What I have mentioned above is there is no lockout situation with the sampling clock & the sampling clock signal is continuous when verified using DSO.

      Now also the signal tap analyser is showing the discontinuity.

      Is there any issue with the signal tap logic analyser or any other settings i have to do , to tap the high frequency signals.

      Regards,

      Vijesh