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VSA00's avatar
VSA00
Icon for New Contributor rankNew Contributor
6 years ago

Error in Signal Tap Logic Analyzer

Hi, I am trying to read a continuous clock signal (125MHz) via IO pin (Bank 8A ,Pin no: L8 ,Pin Name: IO_8A_L8/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T57P) on my custom made cyclone v fpga board. FPGA : Cyc...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Now also the signal tap analyser is showing the discontinuity -- This may be due to the board issue. may be signal integrity issue .