Error: Differential I/O input pin clkin_125 is assigned to a non differential locati

Did you check if it's solved in Quartus V11? Otherwise you should contact Altera support.

I don't no if the solution told in the support note may be suitable for your design.

Unfortunately I have to use just Quartus v10.1 SP1 for this design. There are many different people / blocks involved and so it would not be easy to upgrade to v11.

The "solution" present in Altera support site does not seem to me to be a solution.

Any suggestion is more than welcomed.

Hi thepancake,

thanks for your reply. Could you please provide me with more detail about how exactly to do that?

Thanks a lot

AG

-use the MegaWizard to make a single channel ALTGX with a 125 MHz ref clock and put it into PRBS or BIST mode. all of the other settings shouldn't matter

-use the MegaWizard to make an ALTGX_RECONFIG. i think default settings are fine

-instantiate each block. feed the ALTGX refclk the 125MHz clock. feed all of the reconfig clk and cal clk to the on board 50 MHz oscillator

-connect the ALTGX block to the relevant ports on the ALTGX block. there should be data to reconfig, from reconfig, and possibly a busy signal

-the BIST/PRBS will have pass/fail outputs, those can probably float

-try a compilation, hopefully it works

-if it works you can use the 125 MHz clock elsewhere

stepping back, can't you use the 50 MHz or 100 MHz clock and a PLL to get 125 MHz?

Hi thepancake,

thanks so much for your detailed reply.

I instantiated a ALT_GX block basically with its default properties.

Then I connected all its clocks to the 125MHz clock coming from outside the FPGA.

All its other pins were set as virtual, apart from the ones that generated an error if set as virtual.

In this way Quartus compiles and I am using the 125MHz for the rest of my design (where it is actually required).

The board contains two local oscillators but they are not so good, that is why I want to use an external clock.

Thanks again

AG