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Honored ContributorEP4SGX530 dev board TSE link failure
Hi,
I've been working on integrating a TSE (10/100/1000Mb Ethernet MAC with 1000MASE-X/SGMII PCS) with internal FIFOs and SGMII bridge enabled into a large project. I am using the EP4SGX530 development board and connecting the board via ethernet cable to my PC. The TSE component is driven by a hosting NIOS which sets the connection using noDHCP and sets a static IP address. I started this project in Quartus version 11.1 but have updated to version 14.1.1 (Build 190) and have found this to be a far more stable TSE component. I have working on this for a very long time and read many forum entries but still cannot guarantee link connectivity on .sof upload. My problem is that when I compile my project the whole connection either works and I can interact with the board via ethernet or fails to achieve auto-negotiation on loading of the .sof file and cannot be rectified by software, Eclipse, after the fact. I have output the autonegotiation and link snychronisation signals eth_tse_status_led_connection_an and eth_tse_status_led_connection_link to LED's, they show link synchronisation but no auto-negotiation. Between compilations I would have only implemented minor changes to the vhdl code that shouldn't effect the operation of the TSE component. Since this is occuring I suspect my problem is related to either pin loading assignment requirements or timing constraints on the project. The timing constraints related to the ethernet connection are: # **************************************************************# Time Information# ************************************************************** set_time_format -unit ns -decimal_places 3# **************************************************************# Create Clock# **************************************************************# Clock constraints create_clock -name {clk_50MHz} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clkin_50}] create_clock -name {clk_100MHz} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clkin_100}] create_clock -name {clk_125MHz} -period 8.000 -waveform { 0.000 4.000 } [get_ports {clkin_125}] create_clock -name {hsma_clk_in_p1} -period 8.000 -waveform { 0.000 4.000 } [get_ports {hsma_clk_in_p1}] create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] set Top_clkin_50 clk_50MHz set Top_clkin_100 clk_100MHz set Top_clkin_125 clk_125MHz set LVDS_clkin_125 hsma_clk_in_p1# **************************************************************# Create Generated Clock# **************************************************************# # Derive all pll clocks derive_pll_clocks -create_base_clocks derive_clock_uncertainty # **************************************************************# Constrain SGMII interface clocks# ************************************************************** set TseSgmii_lvds_1250_Clock *|ALTLVDS_RX_component|auto_generated|*|clk[0] set TseSgmii_lvds_125_Clock *|ALTLVDS_RX_component|auto_generated|*|clk[1] set TseSgmii_lvds_rx_Clock *|ALTLVDS_RX_component|auto_generated|rx[0]|clk0 # **************************************************************# Set Asynchronous Clock Groups# ************************************************************** set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] set_clock_groups -asynchronous -group {clk_125MHz} -group {hsma_clk_in_p1} -group {*|eth_tse|i_tse_pcs_0|the_altera_tse_pma_lvds_rx|ALTLVDS_RX_component|auto_generated|pll|clk[0] *|eth_tse|i_tse_pcs_0|the_altera_tse_pma_lvds_rx|ALTLVDS_RX_component|auto_generated|rx[0]|clk0} set_clock_groups -exclusive -group [get_clocks $Top_clkin_50 ] -group [get_clocks $Top_clkin_100 ] -group [get_clocks $Top_clkin_125 ] -group [get_clocks $TseSgmii_lvds_1250_Clock ] -group [get_clocks $TseSgmii_lvds_125_Clock ] -group [get_clocks $TseSgmii_lvds_rx_Clock ] -group [get_clocks $LVDS_clkin_125 ] # **************************************************************# Asynchronous I/O# **************************************************************# Asynchronous inputs set_false_path -to [get_ports {enet_resetn}] # **************************************************************# TSE MAC# ************************************************************** set_min_delay 2 -from * -to [get_ports {enet_mdc enet_mdio}] set_max_delay 10 -from * -to [get_ports {enet_mdc enet_mdio}] set_min_delay 0 -from [get_ports {enet_mdio}] -to * set_max_delay 6 -from [get_ports {enet_mdio}] -to * These result in all ports being constrained and no timing violations occuring. The assignments set in the .qsf file related to the ethernet component are: set_global_assignment -name FMAX_REQUIREMENT "125 MHz" -section_id top_rx_clk_to_the_tse_mac set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id top_rx_clk_to_the_tse_mac set_global_assignment -name FMAX_REQUIREMENT "125 MHz" -section_id top_tx_clk_to_the_tse_mac set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id top_tx_clk_to_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_m_rx_col_to_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_m_rx_crs_to_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_m_rx_d_to_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_m_rx_en_to_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_m_rx_err_to_the_tse_mac set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to top_m_tx_d_from_the_tse_mac set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to top_m_tx_en_from_the_tse_mac set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to top_m_tx_err_from_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_rx_control_to_the_tse_mac set_instance_assignment -name FAST_INPUT_REGISTER ON -to top_rgmii_in_to_the_tse_mac set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to top_tx_control_from_the_tse_mac set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to top_rgmii_out_from_the_tse_mac set_instance_assignment -name CLOCK_SETTINGS top_rx_clk_to_the_tse_mac -to top_rx_clk_to_the_tse_mac set_instance_assignment -name CLOCK_SETTINGS top_tx_clk_to_the_tse_mac -to top_tx_clk_to_the_tse_mac set_instance_assignment -name MULTICYCLE 5 -from "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*" -to * set_instance_assignment -name MULTICYCLE 5 -from "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*" -to * set_instance_assignment -name MULTICYCLE 5 -from * -to "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*" set_instance_assignment -name MULTICYCLE 5 -from "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|half_duplex_ena_reg2" -to * set_instance_assignment -name TPD_REQUIREMENT "7 ns" -from "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft" -to "*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*" set_instance_assignment -name TPD_REQUIREMENT "7 ns" -from "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft" -to "*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*" set_instance_assignment -name TPD_REQUIREMENT "7 ns" -from "*|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg" -to "*|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*" These were placed automatically when integrating the TSE component into the project and I have not altered them. When the link works I can investigate the PCS register space via Eclipse and find all parameters as they should be. When the link fails it seems that the device_partner_ability is not stored in the PCS register space. Can anyone help with the timing constraints and loading assignment requirements for this? Thanks in advance, Cindy
