EP4SGX530 dev board TSE link failure

Well I've got something working and it is all to do with the timing constraints file. Here's how I fixed it.

1. Using a full compilation I editted the sdc file to remove clocks from the set_clocks_group -exclusive set until I had

set_clock_groups

-exclusive

-group [get_clocks $Top_clkin_50 ]

-group [get_clocks $Top_clkin_100 ]

-group [get_clocks $Top_clkin_125 ]

-group [get_clocks $LVDS_clkin_125 ]

This resulted in a timing violation on the LVDS registers for the TSE component.

2. Added timing constraints to the sdc file to bound the paths that had produced timing violations

Then.

3. Recompiled to generate a new fit that would meet the new timing constraints

Result: Ethernet connects every time :)

I hope someone out there finds this useful