huan_wang
New Contributor
New ContributorDual Configuration Intel FPGA IP Core
hello
I'm sorry, I can't reply to your answer. Is this link: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Dual-Configuration-Intel-FPGA-IP-Core/m-p/1514837.
I don't know how to reply, click the reply button, there is no response.
About using MAX10M08SAU169I7G to implement remote update function.
1. How should I connect the config_sel pin in my schematic?
2. I try to change state1: write=1; address= 0x01; writedata= 0x01; , but again, you can't switch to factory image.
3. I read read=1; address= 0x03; , but avmm_rcv_readdata is always 0. I can't detect the busy signal becoming high.
I don't know how to correctly use Dual Configuration Intel FPGA IP Core, can you write a design program for me?
