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huan_wang's avatar
huan_wang
Icon for New Contributor rankNew Contributor
2 years ago

Dual Configuration Intel FPGA IP Core

hello I'm sorry, I can't reply to your answer. Is this link: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Dual-Configuration-Intel-FPGA-IP-Core/m-p/1514837. I don't know how to reply...
Fpga Devkit
WZ2's avatar
WZ2
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2 years ago

Hi Huan,

For MAX 10’s config_sel: This is a dual-purpose pin. Use this pin to choose the configuration image in the dual-configuration images mode.

If the CONFIG_SEL pin is set to low, the first configuration image is configuration image 0. If the CONFIG_SEL pin is set to high, the first configuration image is configuration image 1.

This pin is read before user mode and before the nSTATUS pin is asserted.

More info can refer this document: https://www.intel.com/content/www/us/en/docs/programmable/683232/current/configuration-jtag-pins.html

According to your description: I doubt the correctness of your use of IP because of the no response of readdata. Do u try to read back the data in 0x01?

Here is a demo of RSU of MAX10. You can refer it: https://www.intel.com/content/www/us/en/design-example/714746/max-10-i2c-remote-system-update-example.html

Best regards,

WZ