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prabhu1's avatar
prabhu1
Icon for New Contributor rankNew Contributor
1 year ago

Differential LVDS output clock voltage level settings

Hi,

I am doing this test on development board : cycloneVE_5cefa7f31_fpga_v12_1_1_0

Pins _HSMC_TX_D_P0, HSMC_TX_D_N0 in bank 4( power 2_5v) are used and they are defined as LVDS (output). I am using differential probe (x50). Oscilloscope shows 5Vp_p.

The LVDS swing expected is 300mV. If the output swing measured was 5V, then there is something wrong in the set up or configuration ?

Board Debug

3 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Hi,
    simple fault, LVDS output needs 100 ohm differential termination to see nominal level of 340 mV.
  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

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  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Please follow FvM suggestion to fix your LVDS issue.


    regards,

    Farabi