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fpga_nick's avatar
fpga_nick
Icon for New Contributor rankNew Contributor
7 months ago

Did I need to set a proper pin assignment if I running a simulation ?

I am trying to run a design example simulation for AGIB027R29A1E2VR3, F-tile. Quartus version v23.3 , Questasim 2023-2. But the target devkit with proper pin selection only available for F-series...
Board Debug
Fpga Devkit
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
7 months ago

RTL simulation is used to check your design functionality. Pin assignment is not required. You only need to run the Analysis and Synthesis successfully.

You may try the example design provided in the user guide to further understand the simulation flow.

https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/quick-start.html


Additionally, could you file a new forum case for your follow up question on the compilation error message?

This is for tracking purpose. Btw, the screenshot resolution is too low to view.


Regards,

Richard Tan