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matif1's avatar
matif1
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5 years ago

Design not found for Transceiver Design Flow Level 2 - The Avalon MM Master

Can you please share design of Transceiver Design Flow Level 2 - The Avalon MM Master? It is not available on your website

5 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    As I understand it, you have some inquiries related to a design. Would you mind to further elaborate or refer me to the "Transceiver Design Flow Level 2 - The Avalon MM Master" that you are referring to? Some link will be helpful for me to further probe from there.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    As I look into the page, seems like it is ported from wiki previously. I believe the attachment that you are referring to are previously stored in alterawiki. Since the alterawiki is no longer accessible, thus, we are unable to access the attachment or link. Sorry for the inconvenience.

    Probably you could further elaborate on the specific issue that you are encountering when creating a XCVR design so that I could further assist you?

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • matif1's avatar
      matif1
      Icon for New Contributor rankNew Contributor
      5 years ago

      I have cyclone V sockit board SoC (5CSXFC6D6F31C8ES). I am trying to set up SCVR custom phy ip core. Whenever I try to enter FPGA Fabric Transceiver Interface width of 20 and compile my design, I get the error "Error: Standard RX/TX PCS Parameter 'hd_pcs8g_digi_rx/tx_byte_deserializer' is set to an illegal value of 'en_bds/bs_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom" I saw on this link suggestion from intel (https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03172014_8.html) but I need to use FPGA Fabric transceiver interface width of 20. SO please guide me what can I do?

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    As I understand it, you encounter some error related to the KDB solution rd03172014_8. As I look into the KDB and also the CV device handbook, it seems like the CV device with -6 XCVR speed grade and -8 core speed grade does not support Byte SERDES when the PCS-PMA width =16/20.

    You may try to disable the Byte SERDES to proceed. If need Byte SERDES + PCS-PMA width =16/20, you will need to look for other CV devices. Sorry for the inconvenience.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin