New ContributorI am referring to the document AN 882 [1] [2] ("Using ADI AD9217 with Intel® Stratix® 10 Devices"). The document refers to a design for AD9127 on the Intel Stratix 10 H-Tile Signal Integrity Development.
Is the design provided with the board, or is there a way that Intel could provide it?
[1] https://www.intel.com/programmable/technical-pdfs/683700.pdf
Regular ContributorHi,
The functionality of the design in AN 882 is tested on the Stratix 10 dev kit: Intel® Stratix® 10 GX Signal Integrity Development Kit. You may contact local Intel sales representative if you wish to purchase the board.
Regards
New ContributorHi Ash,
Thank you for your answer.
Do you think the design would be part of the Intel Stratix 10 GX Signal Integrity Development Kit? Because I could not find it so far.
Regular ContributorHi,
The design can be downloaded from the example design link that you mentioned earlier in your description. Board is to be separately purchased and design should be configured in the FPGA on board. Required cables will be provided with the dev kit.
Regards
New ContributorHi,
Thank you for your reply. I went through the documentation [1] thoroughly, but I wasn't able to locate the link to the example design. Could you indicate the link, or provide the example design hands-on?
Thank you.
Regular ContributorHi,
I have requested for the design files. I will let you know as soon as I hear from the concerned members.
Regards
Regular ContributorHi,
Unfortunately the files for AN882 are missing and nobody is able to locate them. It was a very old design. So, I will not be able to provide you the files. Sorry for the inconvenience.
However, you may try to use other example designs to bring up the XCVR lanes through loopback. One example, Intel® Stratix® 10 FPGA – Ultra Low Latency Ethernet 10G for Intel Devices Reference Design.
Regards
