Design for AD9127 on Intel Stratix 10 H-Tile Signal Integrity Development Kit (AN 882)

Hi,

Unfortunately the files for AN882 are missing and nobody is able to locate them. It was a very old design. So, I will not be able to provide you the files. Sorry for the inconvenience.

However, you may try to use other example designs to bring up the XCVR lanes through loopback. One example, Intel® Stratix® 10 FPGA – Ultra Low Latency Ethernet 10G for Intel Devices Reference Design.

Regards