New ContributorRecently i have worked on probing the FMC in scope and seen a sine wave immediately after programming the FPGA sof having the prbs generator. i want to know the status of FPGA IO's after programing. In qsf file it is mentioned as HSSI IO standard pin mapping.
Super ContributorHi,
after programming, respectively in user mode, IOs are controlled by your design. All assigned IO pins take the state you have defined. Unassigned pins get a default state (e.g. tristated with weak-pullup) specified in Quartus Assignments/Device/Device and Pin Options/Unused Pins.
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Regular ContributorHello,
As per user 'FvM' stated in the previous comment. The answer can be accepted, IO's are controlled by your design. All assigned IO pins take the state you have defined.
Best regards,
Nazrul Naim
Regular ContributorHello,
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Best regards,
Nazrul Naim
