Decode Miller (time delay) encoded data using FPGA

Question

Hello, I am trying to decode a bit stream of miller encoded data using an FPGA but am pretty stuck on where to begin.  Does anyone have any insight on a good way this could be implemented?Thank you.

kennyt_altera · Answer

You can try look into this https://www.researchgate.net/publication/332575342_FPGA_Implementation_of_Park-Miller_Algorithm_to_Generate_Sequence_of_32-Bit_Pseudo_Random_Key_for_Encryption_and_Decryption_of_Plain_Text

https://pdfs.semanticscholar.org/aed7/5426db1ca689a4bfcf6220298f973c2715fc.pdf

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Decode Miller (time delay) encoded data using FPGA

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