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Altera_Forum's avatar
Altera_Forum
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13 years ago

DE2 boards revisions ?

Hello

I am an experienced SoC designer, with only little practice with Altera FPGA.

To start with, I have designed a small circuit (for teaching purpose), that simulates and synthesizes correctly using Quartus II 11.0 (Web edition).

My design is supposed to allow interaction between push buttons, sliders, seven segments and leds.

My problem is the following : only 3 boards out of 9 work as expected. These 3 boards are similar in appearance : they have blue capacitors on the top left. The other 6 not working boards don't have these blue capacitors. The 9 boards have the same Cyclone II references.

So I guess that there are two revisions of the DE2 board, which require specific synthesis parameters or they differ elswhere (deboucing ? tri-states for unused pins ?)

Am I right ? Could you help me ?

Thx

JCLL

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    There are definitely different versions of the DE2 board. I think there may be different hardware revisions of the board with the Cyclone II (EP2C35F672C6), and there are versions of the board with larger FPGAs (the DE2-70 and DE2-115).

    Here's the pin assignments script I use for my Cyclone II DE2 board. You could compare it to yours and see if there is a difference.

    Have you looked on Terasic's web site for details? I have an archive of old Terasic zips/CDROM images on hard-drive at work. I can send the schematic for this board if you wanted it.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello Dave

    Thx for the reply. In your file I read :

    set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

    Is this a recommended design rule for Altera boards ? I was suspecting something like that (that I didn't apply).

    Thx again

    JCLL
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    In your file I read :

    set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

    Is this a recommended design rule for Altera boards ? I was suspecting something like that (that I didn't apply).

    --- Quote End ---

    Yes, absolutely.

    If you do not have this setting enabled, and Quartus defaults to driving unused outputs to ground (as it used to in earlier versions), then you may cause damage to your hardware.

    I typically create a top-level design that has all pins used on the PCB. If I do not use a particular interface in a design, then I drive the unused interfaces appropriately, eg., deassert chip selects, drive resets to unused devices active, etc.

    Cheers,

    Dave