DE1SoC (Cyclone 5), SDRAM sharing between HPS and FPGA

I'm trying to share read and write access to the SDRAM between HPS and FPGA of a DE1SoC Dev board (Cyclone 5). Attached is the system I created in Platform Designer 19.1. Basically, I have an AXI4 from SpatialIP (an IP I created) connected to an AXI4 Master to AXI3 translator, and then to the fpga_sdram bridge on the HPS. After testing on the board, I find that BVALID never asserts even though I asserted WVALID, WREADY and WLAST for 1 cycle from the AXI Master, and BREADY is always high. On Cyclone V, what would cause the DRAM controller to not assert BVALID? Do I need to do any extra setups in order to enable the fpga2sdram connection? Am I missing anything here?

Thanks!