DE10-Nano PLL Maximum output frequency

I am working with the DE10-nano development board that is utilizing the Cyclone V (5CSEBA6U23I7) FPGA and the Quartus Prime Version 20.1.1 build to generate a 1.6 GHz PLL output using the PLL Intel FPGA IP block form the IP catalog. According to Table 31 of the Cyclone V datasheet I should be able to achieve between 600 and 1600 MHz, however I am only able to achieve about 700 MHz. Does anybody know why this may be happening?

Any assistance would be greatly appreciated!