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Yakov1's avatar
Yakov1
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4 years ago
Solved

DE10-Nano PLL Maximum output frequency

I am working with the DE10-nano development board that is utilizing the Cyclone V (5CSEBA6U23I7) FPGA and the Quartus Prime Version 20.1.1 build to generate a 1.6 GHz PLL output using the PLL Intel F...
  • Ash_R_Intel's avatar
    Ash_R_Intel
    4 years ago

    Hi,

    The 600MHz to 1600MHz is the VCO frequency range and not the PLL generated output clock. As per the datasheet, it can generate max of 667MHz or 550MHz depending on where you are connecting the clock to.


    Regards


Yakov1's avatar
Yakov1
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4 years ago

Thank you for the clarification!