New Contributor
ContributorHi,
Before we continue investigate, may i know which baremetal application version (hwlib) are you using?
and which link are you refer for your design example?
Thank you,
New ContributorI have identified the reason. In fact, I found that using the SignalTap program the device, as well as converting the SOF to RBF and automatically programming it during Linux boot, result in different SDRAM controller response signals.
My speculation is that when using SignalTap to program the device, the DDR3 SDRAM might be in standby mode or not operational. This means that the SDRAM controller cannot complete the requested write task, leading to the waitrequest signal being constantly high. On the other hand, the Linux system automatically initializes the DDR3 SDRAM, ensuring that everything I'm requesting operates smoothly. The only limitation is that I'm unable to observe the signal performance through SignalTap.
However, of course, everything is just my speculation. I don't have enough evidence to prove this matter.
I am a beginner in FPGA, so I have very little knowledge about what you mentioned regarding "hwlib". I don't know how to properly query the version I am using. All of my builds come from this GitHub repository:
https://github.com/zangman/de10-nano/tree/master
In short, what I want to do is read RF signals through an ADC, digitize the data, and write it into half of the SDRAM space as a buffer because the ADC operates at a high speed. At the same time, I want to run an embedded Linux system on the HPS. Within this Linux system, I aim to use BusyBox to query the ADC digitized data that has been written into the SDRAM.
In fact, I have achieved this already, and I have also speculated about why there is a write occurring every 6 Avalon Master clock cycles. Now, I just want to clarify the details behind it.
Thank you, and I apologize if my explanation was not thorough enough. I'm more than willing to provide additional clarification if needed. If you have any insights about this ADC write task or the technical details behind the 6 Avalon Master clock cycles to SDRAM controller, I would greatly appreciate it if you could explain further. Your assistance is sincerely appreciated!
