DE10-LITE and RAM: 1-PORT IP - WREN inverted on actual hardware?

I'm starting out with FPGA's on a DE10-LITE and while trying out a RAM: 1-PORT IP on a simple project to put the memory output from a 10 port RAM onto the LEDs, with the 10 switches as input to the RAM IP, I noticed what worked fine in the simulator RTL and Gate level worked very differently on the real hardware, specifically I found I had to hold down the button tied to WREN to prevent writing and keep data in memory addresses, and release to write. However, in the simulations if I try to repeat this behavior, it doesn't work at all.

Any ideas what could be going on here? Advice on how I could debug and rectify this problem? Or should I abandon the RAM IP's and try to use the RAM Templates instead?

Thanks for any help in advance!