de0-Nano SPI slave implementation VHDL

Hi all,

I just got hold of a DE0-Nano board. I'm trying to implement a very simple SPI (nano as slave). At the moment I just want to be able to continuously latch in a value, and then read it back out using an MCU, confirming there is communication at a basic level. I have assigned pins (just using the pin planner, naming the GPIO's im using) hooked up and programmed the board, I know my MCU SPI code works, but I notice I'm not getting anything on my MISO at all.. despite correct operation using a vector waveform analysis.

I'm wondering if there are additional steps to do with configuring the pins that I have not taken, or if I need to enable some system clock? I have some experience using VHDL and the DE0-Nano, but that was at uni, using templates provided.

Code is below for reference. All im doing is looking for the rising edge of what would be SCLK on a GPIO input, and shifting through bits while device select is low.

Thanks for any help, I'll be busy reading the instruction manual in the mean time.

Cheers, Chris.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI1 is
port
(
	RESET : in std_logic;
	
	SERIAL_CLK : in std_logic;
	SERIAL_IN : in std_logic;
	SLAVE_SELECT : in std_logic;
	
	PARALLEL_OUT : out std_logic_vector(7 downto 0) := "00000000";
	SERIAL_OUT : out std_logic := '0'
);
end entity SPI1;
architecture v1 of SPI1 is
	signal DATA : std_logic_vector(7 downto 0) := "00000000";
	signal BIT_COUNT : integer range 0 to 8 := 0;
	type LATCH is (enabled, disabled);
	signal LATCH_STATE : LATCH := disabled;
	
begin
	process(SERIAL_CLK, RESET, SLAVE_SELECT)
	
	begin
	
		
		if(rising_edge(SERIAL_CLK)) then
			
			if(SLAVE_SELECT = '0') then
					
				if(BIT_COUNT <=7) then
				
					SERIAL_OUT <= DATA(7);
					LATCH_STATE <= disabled;
					DATA <= DATA(6 downto 0) & SERIAL_IN;
					BIT_COUNT <= BIT_COUNT + 1;
				
				end if;
					
			elsif(SLAVE_SELECT='1' and BIT_COUNT = 8) then
			
				BIT_COUNT <= 0;
				SERIAL_OUT <= '0';
				LATCH_STATE <= enabled;
			
			end if;
		end if;
		
	end process;
	
	process(LATCH_STATE)
	
	begin
	
		if(LATCH_STATE = enabled) then
			PARALLEL_OUT <= DATA( 7 downto 0);
		end if;
	end process;
	
end architecture v1;