DDR2 SDRAM termination

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Termination is already included inside the DDR2 SDRAM chips.

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Not exactly. Dynamic termination (ODT) is present for DQ and DQS line during data write. In a multi-bank DIMM module, the on-chip termination of the inactive chip can be switched on, while the other chip is selected for read. So you effectively get a SSTL CLASS I termination scheme for DQ and DQS without external termination resistors. The address and control lines have no on-chip termination. External resistors are required for it to achieve SSTL class I. Altera has an application note AN408, that compares achievable signal quality for different termination schemes. Also RAM manufacturers, e.g. Micron have application notes about DDR II system design. Furthermore Altera AN445 is particularly dedicated to Cyclone III DDR RAM interfaces.

Just another question.

In AN427 Altera set the mem ODT as "disabled" for the MT47H32M16CC-3 ddr2 DRAM.

As long as I wanto to use their assignment in another design, I should set my memory ODT as disabled ?

Another question, if possible: where can I read more about SSTL classes?

best regards

Phate.

I'm currently designing a board with an Cyclone III or Cyclone IV and attached DDR2 memory.

Is there a recent reference design (layout, schematic, quartus design) available which corresponds to the recommendations stated in "External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines" (emi_plan.pdf).

In particular, I'm interested in the termination scheme. Which termination resistor is really needed and where has it to be placed on the pcb?

I thougth that using ODT and OCT you shouldn't need to place resistors on your pcb.

Maybe I am wrong.