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Termination is already included inside the DDR2 SDRAM chips.
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Not exactly. Dynamic termination (ODT) is present for DQ and DQS line during data write. In a multi-bank DIMM module, the on-chip termination of the inactive chip can be switched on, while the other chip is selected for read. So you effectively get a SSTL CLASS I termination scheme for DQ and DQS without external termination resistors. The address and control lines have no on-chip termination. External resistors are required for it to achieve SSTL class I. Altera has an application note AN408, that compares achievable signal quality for different termination schemes. Also RAM manufacturers, e.g. Micron have application notes about DDR II system design. Furthermore Altera AN445 is particularly dedicated to Cyclone III DDR RAM interfaces.
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