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Altera_Forum
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16 years ago

DDR2-SDRAM on Cyclone III DSP Kit (no NIOS)

Hi,

I am using the dsp development kit, cyclone iii edition (http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html).

I wanted to use the DDR2-SDRAM but unfortunately there is no design example for it. So I used the IP-Core called "DDR2 SDRAM High Performance Controller". There I chose Micron MT47H32M16CC-3 x4 + MT47H32M8BP-3 x1, because that is the same like in the Cyclone III Reference Manual. Then I wanted to connect the FPGA pins to the IP-Core, but I wondered where to connect ddr2top_a[15..0], ddr2bot_a[15..0], ddr2top_ba[2..0], ddr2bot_ba[2..0], etc.

Because on the IP-Core there are only buses called mem_addr[12..0] and mem_ba[1..0].

I can change Bank Address Width from 2 Bit to 3 Bit and Row Address Width from 13 Bit to 16 Bit, so it matches, but I still have the problem that I have only one output bus(mem_addr) at the IP-Core for the two buses Top and Bottom.

Has anybody the same board and used the DDR2-SDRAM with the FPGA (and without NIOS) ?

Thanks.

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi stefan! Greetings from Brazil.

    I just read your topic where you inquired about how to use the SDRAM controller without Nios... have you been able to do so successfully?

    I have the same problem as you did -- I need more memory, but I don't want to use Nios. Actually, it is essential that I do not use Nios, since I am preparing a MIPS processor Verilog HDL design for a Computer Organization and Architecture class.

    So far we have been able to do good things with our design -- even simple speech processing and a simple Space Invaders style video game! But for our final projects to reach the next level, we need to provide the students with enough memory to store media.

    I would be really thankful if you could give me some pointers! All the material I find online assumes you use Nios.

    Thank you for your attention,

    George Brindeiro

    University of Brasília
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Stefan_,

    Did you ever have resolution on this?

    I am having a similar problem with local_ready from the controller going low and staying low. I know that the controller does get past the calibration stage and starts doing reads and writes. Then at some point, the local ready goes low and the controller stops accepting anything new. If you figured anything out in your design and don't mind sharing, it could be very helpful.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    please check the clocks! This already be discussed here.

    The ddr2_sys clock is not the same like the input clock of DDR2 controller! So if you have 100 MHz clk_in and then use some signals derived from clk_in (like begin_burst, local_write or so), this causes this problem. For all control signals (local_...) you have to use the ddr2_sys clock, which is generatet by ddr2_controller.

    Kest