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Altera_Forum
Honored Contributor
Honored ContributorDDR2-SDRAM on Cyclone III DSP Kit (no NIOS)
Hi, I am using the dsp development kit, cyclone iii edition (http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html). I wanted to use the DDR2-SDRAM but unfortunately there is no ...
Altera_ForumHonored Contributor
Honored Contributorplease check the clocks! This already be discussed here.
The ddr2_sys clock is not the same like the input clock of DDR2 controller! So if you have 100 MHz clk_in and then use some signals derived from clk_in (like begin_burst, local_write or so), this causes this problem. For all control signals (local_...) you have to use the ddr2_sys clock, which is generatet by ddr2_controller. Kest
