Data from FPGA to host

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For example it uses master_read_32 when reading the memory but I can't find what this command is doing.

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Often, you can use google to answer small questions like this (just plugin the function name to google). See page 10-44 (the 197th page of the PDF) of http://www.altera.com/literature/hb/qts/qts_qii5v3.pdf

Many thanks. And I see "master_read_to_file" that will be useful to create a file (although it's a binary file and I need to think of that).

So the system console is able to directly speak with the sdram from simple commands of the user?

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So the system console is able to directly speak with the sdram from simple commands of the user?

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It isn't "direct" as there is a relatively complicated and sophisticated path between your keyboard and the pins on the SDRAM chip, but yes it does allow you to read/write SDRAM data when all the right pieces are in place. And it can do a lot more than that.

Altera offers free training videos and documentation that have introductions to these tools.

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And I see "master_read_to_file" that will be useful to create a file (although it's a binary file and I need to think of that).

So the system console is able to directly speak with the sdram from simple commands of the user?

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Look at the block diagram here;

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

(Read the tutorial too!)

Cheers,

Dave

Hi,

@Dave

I started your altera_jtag_to_avalon_mm_tutorial but not finished it yet. For now I have some questions about the de0_nano_sdram tutorial:

- Why is there a PLL with two outputs (c0 and c1) at the same frequency? Isn't it possible to use the same clock for qsys design and for the sdram?

- Why 100MHz? Couldn't we use the 50MHz oscillator directly?

- What need is the synchronizer? The reset couldn't be asynchronous?

- There's a sld_hub component in the project. What is it? I can't see this component in the verilog code, why?

And also I wonder why you're not working for Altera but you seem to create good tutorials. You answer many questions on alteraforum. It's really great for beginners (like me), but why? and were do you work? and how do you have so much time to spend for us?

@ted

Thanks for the explanation.

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I started your altera_jtag_to_avalon_mm_tutorial but not finished it yet. For now I have some questions about the de0_nano_sdram tutorial:

- Why is there a PLL with two outputs (c0 and c1) at the same frequency? Isn't it possible to use the same clock for qsys design and for the sdram?

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There are two 100MHz clocks; one goes to the FPGA logic, the other goes to the SDRAM device (its an output clock).

If you use one clock, the timing analysis of the SDRAM interface would show that it fails timing. By using two clocks, it is possible to meet timing by adjusting the phase of the clock that goes to the SDRAM. Take a look at TimeQuest once the design is synthesized, and then modify it so that the SDRAM clock inside the design is driven from c0 instead of c1.

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- Why 100MHz? Couldn't we use the 50MHz oscillator directly?

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50MHz would have been too easy :)

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- What need is the synchronizer? The reset couldn't be asynchronous?

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The Quartus handbook has a discussion on why you should use a reset that asserts asynchronously, yet deasserts synchronously. Cliff Cummings also has some nice documents on resets (Google his name).

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- There's a sld_hub component in the project. What is it? I can't see this component in the verilog code, why?

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When you add a JTAG-to-Avalon-MM bridge or a component like SignalTap II an SLD HUB is added to the system.

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And also I wonder why you're not working for Altera but you seem to create good tutorials. You answer many questions on alteraforum. It's really great for beginners (like me), but why? and were do you work? and how do you have so much time to spend for us?

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I work for a university, but live in the middle of nowhere. Take a look at these slide presentations (the first few links);

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

I write the tutorials when I am learning how to use the components myself. I figure if I had trouble understanding Altera's documentation, then others will too, so I post the tutorials to help.

When do I get time to write to the forum? When I'm drinking my coffee ... I guess I drink way to much coffee ... :)

Cheers,

Dave

OK for the PLL, the reset (I'm reading a paper from Cliff Cummings) and the SLD_hub.

Today's questions:

A user can send commands in the system console but I don't know if I can type at a rate of 1kHz! Can the design put values in the sdram by itself (maybe using a NIOS)?

What need is the quartus_stp? What difference with the system_console?

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I work for a university

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Are you a professor or what is your work?

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When do I get time to write to the forum? When I'm drinking my coffee ... I guess I drink way to much coffee ... :)

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LOL

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A user can send commands in the system console but I don't know if I can type at a rate of 1kHz! Can the design put values in the sdram by itself (maybe using a NIOS)?

What need is the quartus_stp? What difference with the system_console?

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You can write a Tcl script that can transfer the data. The "fastest" Tcl method is master_read_memory or master_write_memory. The fastest it can go is about 600kB/s.

You can transfer your data by either writing to one side of a FIFO and reading it via Tcl from the other, or perhaps a slightly easier solution to understand would be to capture a block of samples, and then read them out over Tcl, and then repeat that sequence. The JTAG-to-Avalon-MM tutorial describes how to simulate a Qsys system, so you can always try that too.

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Are you a professor or what is your work?

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I'm an engineer building FPGA-based hardware and high-speed ADC interface logic for radio astronomy signal processing. The slides I linked to show what I build.

Cheers,

Dave

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or perhaps a slightly easier solution to understand would be to capture a block of samples, and then read them out over Tcl, and then repeat that sequence.

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Maybe it seems easier for you but I don't understand this. What does it imply? How does it work?

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Maybe it seems easier for you but I don't understand this. What does it imply? How does it work?

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Have you ever used SignalTap II? If not, go and try to use it. Capture a trace of the signal you are interested in, and then visually look at the traces.

SignalTap II is "just code" and you can duplicate its capture functionality, but rather than displaying the data, you transfer it over JTAG and then analyze the data.

Cheers,

Dave