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Altera_Forum
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11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

OK for the PLL, the reset (I'm reading a paper from Cliff Cummings) and the SLD_hub.

Today's questions:

A user can send commands in the system console but I don't know if I can type at a rate of 1kHz! Can the design put values in the sdram by itself (maybe using a NIOS)?

What need is the quartus_stp? What difference with the system_console?

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I work for a university

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Are you a professor or what is your work?

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When do I get time to write to the forum? When I'm drinking my coffee ... I guess I drink way to much coffee ... :)

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LOL