Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

@Dave

I started your altera_jtag_to_avalon_mm_tutorial but not finished it yet. For now I have some questions about the de0_nano_sdram tutorial:

- Why is there a PLL with two outputs (c0 and c1) at the same frequency? Isn't it possible to use the same clock for qsys design and for the sdram?

- Why 100MHz? Couldn't we use the 50MHz oscillator directly?

- What need is the synchronizer? The reset couldn't be asynchronous?

- There's a sld_hub component in the project. What is it? I can't see this component in the verilog code, why?

And also I wonder why you're not working for Altera but you seem to create good tutorials. You answer many questions on alteraforum. It's really great for beginners (like me), but why? and were do you work? and how do you have so much time to spend for us?

@ted

Thanks for the explanation.