Occasional Contributor
Occasional ContributorOne more update. I spent the last few days creating a very dumb basic bootloader, so that I could: 1. simulate the RTL code in Questasim, and 2. Sample internal nets of the same code using the ISSP function. I ran it on the "very bad" boards I have and on one "mostly bad" board (it fails 1/5 even with my new slightly better Max5 bootloader). I also tried it on fully good known boards. What I found is that the bad boards CVGT FPGA are triggering a "Framing/CRC" error on the bit stream, at RANDOM offsets in the NOR flash memory. IE every reset of the Max5 CPLD fails but fails at a different address in NOR flash. I also had ISSP capture some of the NOR data bytes that the CPLD was about to send to the FPGA config port, around a failure event. The data seemed stable, although not enough samples were captured to guarantee this statement. In short, there is something wrong with the hardware on the bad boards. Note also this dumb basic bootloader runs at 25 mhz, lots of time for the NOR flash output to settle. Altera continues to send out a mix of good/notsogood/bad boards at this point. We will be sending back any that fail normal bootloading for refund/replacement.
Regular Contributor
Hi GordWait,
Thank you for the additional findings and the serial numbers.
We would like to clarify a couple of points to ensure we correctly understand the latest results.
In an earlier update, you mentioned that the factory max5.pof was able to boot the marginal boards, whereas your custom build did not. In the latest update, you noted that some boards do not boot reliably even with the factory image.
Could you please help confirm:
For SN 5CPCIE00100119, 5CPCIE00100129, and 5CPCIE00100262, what is the behavior when using the unmodified factory max5.pof?
For each of the above boards, could you share the MAX V timing report from the corresponding build that was programmed onto the board?
This will help us determine whether the latest observations are still consistent with the timing-margin hypothesis or indicate a different issue.
Thanks.
Occasional ContributorUsing the Altera unmodified factory max5.pof :
The two "Very Bad" boards never boot.
The mostly bad board boots sometimes.
Since the errors are random, and the Altera factory image is smallish, AND the factory max5 has retries enabled, the mostly bad boards can sometimes boot the Altera firmware after several retries. This is of course a complete failure. If Altera's OQC is just - did the board eventually boot? - then the marginal boards can pass even though they have real hardware issues.
The two very bad boards fail for us completely. It is hard to understand how they passed OQC at Altera.
For the timing, I do not have the timing report for the Altera factory max5.pof as someone at Altera compiled it.
BUT since I was able to get some of the new "marginal boards" (not these three bad ones) to boot with our modified standard bootloader (based on the factory build) by improving the timing, AND these new "marginal boards" also boot with my "from scratch" bootloader that runs very conservatively (not based on the Altera PFL core), it does seem like some sort of time critical issue on the part of the latest batches of the boards from Altera.
