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Overstay123's avatar
Overstay123
Icon for New Contributor rankNew Contributor
1 year ago

cyclone v e lvds

Hello, I want to use 5CEFA5 to connect to an adc. The adc has a 250msps clock, 14bit, and 1.8v lvds interface. I want to use fpga to input clock for this adc. I checked the manual and found that vccio of lvds needs 2.5v. I want to know whether this can input clock for adc? The input parameters of this adc are: Internal Common-Mode Bias 0.9V,Differential Input Voltage 0.3-3.6Vp-p, Input Voltage Range 0-1.8V, Input Common-Mode Range is 0.9-1.4V.

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1 Reply

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Hi,
    this is a standard LVDS level specification, the ADC clock input can be well driven by a FPGA clock output with LVDS IO standard.
    Consider that ADC performance will be possible degraded by FPGA PLL jitter. Depending on your ADC application, it may be suggested to derive the ADC clock directly from a low phase noise source.