Forum Discussion
Overstay123
New Contributor
New Contributorcyclone v e lvds
Hello, I want to use 5CEFA5 to connect to an adc. The adc has a 250msps clock, 14bit, and 1.8v lvds interface. I want to use fpga to input clock for this adc. I checked the manual and found that vcci...
FvM
Super Contributor
Super ContributorHi,
this is a standard LVDS level specification, the ADC clock input can be well driven by a FPGA clock output with LVDS IO standard.
Consider that ADC performance will be possible degraded by FPGA PLL jitter. Depending on your ADC application, it may be suggested to derive the ADC clock directly from a low phase noise source.
this is a standard LVDS level specification, the ADC clock input can be well driven by a FPGA clock output with LVDS IO standard.
Consider that ADC performance will be possible degraded by FPGA PLL jitter. Depending on your ADC application, it may be suggested to derive the ADC clock directly from a low phase noise source.
