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New Contributor

4 years ago

Solved

Cyclone V - Differential Pair Pin Assignment 1.5V PCML fitter error

When creating a new Quartus project similar to a demo example, I am trying to place XCVR pins in a blank project and getting an error from the 1.5V PMCL differential pins (HSMC_GXB_RX_p0 and HSMC_GXB_TX_p0 for example).

Why am I getting this fitter error and do I need some minimum of connections to support the differential pins, and if that is the case what is the minimum code I need to declare these pins in a new project so it compiles?

I believe I have the IO standard correctly set to 1.5V PCML and Pins set to the recommended pins in the User's Guide and there are no other pins conflicting that I can see in the QSF file.

Compiler Error:

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (0, 11) to (0, 11), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): HSMC_GXB_TX_p0
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough differential output pin locations available (1 location affected)
Info (175029): pin containing PIN_AE4
Info (175015): The I/O pad HSMC_GXB_TX_p0 is constrained to the location PIN_AE4 due to: User Location Constraints (PIN_AE4)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (0, 14) to (0, 14), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): HSMC_GXB_RX_p0
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough differential input pin locations available (1 location affected)
Info (175029): pin containing PIN_AD2
Info (175015): The I/O pad HSMC_GXB_RX_p0 is constrained to the location PIN_AD2 due to: User Location Constraints (PIN_AD2)
Info (14709): The constrained I/O pad is contained within this pin

.QSF file output:

set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY CPL_HDL
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:00:27 JUNE 13, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE CPL_HDL.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_RX_p0
set_location_assignment PIN_AD2 -to HSMC_GXB_RX_p0
set_location_assignment PIN_AD1 -to "HSMC_GXB_RX_p0(n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to HSMC_GXB_TX_p0
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_CONVST
set_location_assignment PIN_AB22 -to ADC_CONVST
set_location_assignment PIN_AA21 -to ADC_SCK
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_SCK
set_location_assignment PIN_Y10 -to ADC_SDI
set_location_assignment PIN_W10 -to ADC_SDO
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "1.2 V" -to ADC_SDO
set_location_assignment PIN_D7 -to AUD_ADCDAT
set_location_assignment PIN_C7 -to AUD_ADCLRCK
set_location_assignment PIN_E6 -to AUD_BCLK
set_location_assignment PIN_H10 -to AUD_DACDAT
set_location_assignment PIN_G10 -to AUD_DACLRCK
set_location_assignment PIN_D6 -to AUD_XCK
set_location_assignment PIN_R20 -to CLOCK_50_B5B
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_ADCDAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_ADCLRCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_BCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_DACDAT
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_DACLRCK
set_instance_assignment -name IO_STANDARD "2.5 V" -to AUD_XCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_B5B
set_location_assignment PIN_N20 -to CLOCK_50_B6A
set_location_assignment PIN_H12 -to CLOCK_50_B7A
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_B6A
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50_B7A
set_location_assignment PIN_M10 -to CLOCK_50_B8A
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50_B8A
set_location_assignment PIN_U12 -to CLOCK_125_p
set_instance_assignment -name IO_STANDARD LVDS -to CLOCK_125_p
set_location_assignment PIN_V12 -to "CLOCK_125_p(n)"
set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF
set_location_assignment PIN_AE4 -to HSMC_GXB_TX_p0
set_location_assignment PIN_AE3 -to "HSMC_GXB_TX_p0(n)"
set_global_assignment -name SMART_RECOMPILE OFF
set_location_assignment PIN_AB24 -to CPU_RESET_n
set_location_assignment PIN_Y18 -to HEX0[6]
set_location_assignment PIN_Y19 -to HEX0[5]
set_location_assignment PIN_Y20 -to HEX0[4]
set_location_assignment PIN_W18 -to HEX0[3]
set_location_assignment PIN_V19 -to HEX0[0]
set_location_assignment PIN_V18 -to HEX0[1]
set_location_assignment PIN_V17 -to HEX0[2]
set_location_assignment PIN_AA18 -to HEX1[0]
set_location_assignment PIN_AD26 -to HEX1[1]
set_location_assignment PIN_AB19 -to HEX1[2]
set_location_assignment PIN_AE26 -to HEX1[3]
set_location_assignment PIN_AE25 -to HEX1[4]
set_location_assignment PIN_AC19 -to HEX1[5]
set_location_assignment PIN_AF24 -to HEX1[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CPU_RESET_n
set_location_assignment PIN_B7 -to I2C_SCL
set_location_assignment PIN_G11 -to I2C_SDA
set_instance_assignment -name IO_STANDARD "2.5 V" -to I2C_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to I2C_SDA
set_location_assignment PIN_P11 -to KEY[0]
set_location_assignment PIN_P12 -to KEY[1]
set_location_assignment PIN_Y15 -to KEY[2]
set_location_assignment PIN_Y16 -to KEY[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to KEY[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Kshitij_Intel
4 years ago
Hi Terra,

I have told you earlier, you cannot directly connect, Please design custom logic to reconstruct the word. First correct your design then try to compile.

Thank you
Kshitij Goel

25 Replies

Kshitij_Intel
Frequent Contributor
4 years ago
Hi Terra,

It is always recommended to instantiate the XCVR. There is article also https://www.intel.com/content/www/us/en/support/programmable/articles/000077932.html

If still you face any issues, please share your project with mentioning the environment details and device details.

Thank you
Kshitij Goel
TerraX
New Contributor
4 years ago
Hi, I am using Quartus Prime Lite 16.1 version with a Cyclone V dev board called C5G Starter Kit from Terasic. The exact FPGA device is a Cyclone V 5CGXFC5C6F27C7. I am also using the HSMC (High Density mezzanine connector) to hook up an expansion card. The expansion card has HD-SDI BNC connectors In and Out that are routed through the FPGA.

The goal is to short the HSMC_GXB_RX pin to the HSMC_GXB_TX pin in order to make a "straight through" test for the signal. The HD-SDI signal is being generated off the dev boards and, eventually, the FPGA only needs to route the SDI input to one of the two Tx output pairs as a switch.

In Quartus, I cannot find an IP named ALTGXB anywhere in the catalog. On the ALTGXB Intel page it does not say how to install this for a Cyclone V device. Can you help?

I also searched the IP catalog for XCVR but there is nothing named that. I see SDI v16.1? But these are time sensitive blocks so it may be more fancy than what I need? I am looking for a simple buffer to link the GXB_RX pair to the GXB_Tx pins. Thank you.

-Terra
Kshitij_Intel
Frequent Contributor
4 years ago
Hi,

Can you please share your project.

Thank you
Kshitij Goel
Kshitij_Intel
Frequent Contributor
4 years ago
Hi,

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you
KG
TerraX
New Contributor
4 years ago
My project is empty except for pin locations, which file extensions are what you want to see?

I am trying to figure out what is the minimum I need to connect the pins together.

My goal is just to make a straight through connection between these pins:

INPUT: HSMC_GXB_RX[0] on PIN_AD2 (HD-SDI in)

OUTPUT: HSMC_GXB_TX[0] on PIN_AE4 (HD-SDI out)

Any suggestions would be very helpful. I am using the Terasic Developement board C5G with an SDI mezzanine breakout board so I can't really move the pins around too much.

The signal that I am passing through is HD-SDI. (It is NOT a dual link)
Kshitij_Intel
Frequent Contributor
4 years ago
Hi,

Refer to the UG, ALTGXB is transceiver block and which needs to be instantiated.

SDI IP Core User Guide

Thank you

Kshitij Goel
TerraX
New Contributor
4 years ago
OK, but do I use SDI II or SDI v16.1?

Also, do I instantiate just one, or do I need a separate one for the RX & TX?

How do I provide the 1.485G Clock?
TerraX
New Contributor
4 years ago
Do I need the protocol blocks for a straight through connection or can I do transceiver only?
TerraX
New Contributor
4 years ago
I tried to add SDI_v16.1 as a generate Transceiver only Bidirectional IP Core. Then I added a Altera PLL and created an output clock of 74.25MHz.

I have Quartus setup to add the generated files to the Project automatically, but it doesn't seem to compile.

The Compile errors I am getting now are:

Info (12021): Found 1 design units, including 1 entities, in source file sdi-library/sdi_rate_detector.v
Info (12023): Found entity 1: sdi_rate_detector
Info (12128): Elaborating entity "sdi_rate_detector" for hierarchy "SDI_v16_t:SDI_v16_Bidirectional1|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|sdi_rate_detector:sdi_receiver_rate_detector.rate_detector_inst"
Error (12006): Node instance "gen_duplex_native.cv_nativephy_inst" instantiates undefined entity "altera_xcvr_native_av". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "gen_duplex_native.tx_xcvr_reset_control_inst" instantiates undefined entity "altera_xcvr_reset_control". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "gen_duplex_native.rx_xcvr_reset_control_inst" instantiates undefined entity "altera_xcvr_reset_control". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 30 warnings
Error: Peak virtual memory: 4795 megabytes
Error: Processing ended: Tue Jul 19 19:00:45 2022
Error: Elapsed time: 00:00:10
Error: Total CPU time (on all processors): 00:00:19
Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 30 warnings

The code from my top.v file is:

module C5G_HSMC_XCVR_LOOPBACK_TEST(

///////// ADC /////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,

///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,

///////// CLOCK /////////
input CLOCK_125_p,
input CLOCK_50_B5B,
input CLOCK_50_B6A,
input CLOCK_50_B7A,
input CLOCK_50_B8A,

///////// CPU /////////
input CPU_RESET_n,

///////// GPIO /////////
inout [35:0] GPIO,

///////// HDMI /////////
output HDMI_TX_CLK,
output [23:0] HDMI_TX_D,
output HDMI_TX_DE,
output HDMI_TX_HS,
input HDMI_TX_INT,
output HDMI_TX_VS,

///////// HEX0 /////////
output [6:0] HEX0,

///////// HEX1 /////////
output [6:0] HEX1,

///////// HSMC /////////
/*
input HSMC_CLKIN0,
input [2:1] HSMC_CLKIN_n,
input [2:1] HSMC_CLKIN_p,
output HSMC_CLKOUT0,
output [2:1] HSMC_CLKOUT_n,
output [2:1] HSMC_CLKOUT_p,
inout [3:0] HSMC_D,
*/
input [0:0] HSMC_GXB_RX_p,
output [0:0] HSMC_GXB_TX_p,

output HSMC_SDI_Rate_Sel_1,
output HSMC_SDI_Rate_Sel_2,
output HSMC_EQBypass_1,
output HSMC_EQBypass_2,
output HSMC_SDI_CLK_Sel,
output HSMC_SDI_XTAL_Sel,

///////// I2C /////////
output I2C_SCL,
inout I2C_SDA,

///////// KEY /////////
input [3:0] KEY,

///////// LEDG /////////
output [7:0] LEDG,

///////// LEDR /////////
output [9:0] LEDR,

///////// SD /////////
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT,

///////// SRAM /////////
output [17:0] SRAM_A,
output SRAM_CE_n,
inout [15:0] SRAM_D,
output SRAM_LB_n,
output SRAM_OE_n,
output SRAM_UB_n,
output SRAM_WE_n,

///////// SW /////////
input [9:0] SW,

///////// UART /////////
input UART_RX,
output UART_TX
);

//=======================================================
// REG/WIRE declarations
//=======================================================
wire reset_hsmc_xcvr_phy;
wire reset_xcvr_reconfig;
wire [19:0] SDI_Databus20;
wire TRS_First_Word;
wire TRS_Locked = 1'b1;
wire [10:0] Line_Number;
wire CLOCK_148_5MHZ;
wire CLOCK_74_25MHZ;
wire reset1_n;
wire reset2_n;
wire reset_n;

//-----HSMC Daughter Card support
reg SDI_Rate_Sel_1 = 1'b0;
reg SDI_Rate_Sel_2 = 1'b0;
reg EQBypass_1 = 1'b0;
reg EQBypass_2 = 1'b0;
reg SDI_CLK_Sel = 1'b0;
reg SDI_XTAL_Sel = 1'b0;

///////////////////////////////////////
//=======================================================
// assignments
//=======================================================

assign HSMC_EQBypass_1 = EQBypass_1; // RX Cable Equalizer. High = Bypass, Low = Use equalizer.
assign HSMC_EQBypass_2 = EQBypass_2; // RX Cable Equalizer. High = Bypass, Low = Use equalizer.
assign HSMC_SDI_Rate_Sel_1 = SDI_Rate_Sel_1; // TX Cable Driver. High = SD, Low = HD/3G
assign HSMC_SDI_Rate_Sel_2 = SDI_Rate_Sel_2; // TX Cable Driver. High = SD, Low = HD/3G
assign HSMC_SDI_CLK_Sel = SDI_CLK_Sel;
assign HSMC_SDI_XTAL_Sel = SDI_XTAL_Sel;

//=======================================================
// REG/WIRE declarations
//=======================================================

PLL_XCVR XCVR_PLL_1 (
.refclk(CLOCK_50_B7A), // refclk.clk
.rst(~CPU_RESET_n), // reset.reset
.outclk_0(CLOCK_148_5MHZ), // outclk0.clk
.outclk_1(CLOCK_74_25MHZ), // outclk1.clk
.locked(reset_n) // locked.export
);

//---Generated SDI v16.1 IP CORE. Bidirectional. No Protocol block (Transceiver Only).
SDI_v16_t SDI_v16_Bidirectional1 (
.rst_rx ( ~reset_n ),
.rst_tx ( ~reset_n ),
.rx_serial_refclk ( CLOCK_74_25MHZ ), // input must be nominally 1/20th of the serial data rate. This clock trains the internal PLL.
.tx_pclk ( CLOCK_74_25MHZ ),
.tx_serial_refclk ( CLOCK_74_25MHZ ),
.sdi_rx ( HSMC_GXB_RX_p ), // Pin#
.txdata ( SDI_Databus20 ), // input [19:0] 20bits to HD-SDI
.refclk_rate ( 1'b1 ), // Set input to 1 for 148.5-MHz RX serial reference clock, to 0 for a 148.35-MHz receiver serial reference clock.
.rx_protocol_locked ( TRS_Locked ), // input
.rx_xcvr_trs_lock ( TRS_Locked ), // input stays high when valid TRS packets are detected.
.sdi_reconfig_togxb ( ),
.sdi_tx ( HSMC_GXB_TX_p ), // Pin#
.rxdata ( SDI_Databus20 ), // output [19:0] 20bits from HD-SDI
.rx_data_valid_out ( ),
.rx_clk ( CLOCK_74_25MHZ ), // input
.rx_status ( ),
.tx_status ( ),
.detected_rate ( ),
.gxb_tx_clkout ( ),
.sdi_reconfig_fromgxb ( )

);

endmodule
Kshitij_Intel
Frequent Contributor
4 years ago
Hi,

Okay, Share your project .qar, also mention Quartus version used.

Thank you
Kshitij Goel