New ContributorHi Terra,
I have told you earlier, you cannot directly connect, Please design custom logic to reconstruct the word. First correct your design then try to compile.
Thank you
Kshitij Goel
New ContributorI tried to add SDI_v16.1 as a generate Transceiver only Bidirectional IP Core. Then I added a Altera PLL and created an output clock of 74.25MHz.
I have Quartus setup to add the generated files to the Project automatically, but it doesn't seem to compile.
The Compile errors I am getting now are:
The code from my top.v file is:
module C5G_HSMC_XCVR_LOOPBACK_TEST(
///////// ADC /////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
///////// CLOCK /////////
input CLOCK_125_p,
input CLOCK_50_B5B,
input CLOCK_50_B6A,
input CLOCK_50_B7A,
input CLOCK_50_B8A,
///////// CPU /////////
input CPU_RESET_n,
///////// GPIO /////////
inout [35:0] GPIO,
///////// HDMI /////////
output HDMI_TX_CLK,
output [23:0] HDMI_TX_D,
output HDMI_TX_DE,
output HDMI_TX_HS,
input HDMI_TX_INT,
output HDMI_TX_VS,
///////// HEX0 /////////
output [6:0] HEX0,
///////// HEX1 /////////
output [6:0] HEX1,
///////// HSMC /////////
/*
input HSMC_CLKIN0,
input [2:1] HSMC_CLKIN_n,
input [2:1] HSMC_CLKIN_p,
output HSMC_CLKOUT0,
output [2:1] HSMC_CLKOUT_n,
output [2:1] HSMC_CLKOUT_p,
inout [3:0] HSMC_D,
*/
input [0:0] HSMC_GXB_RX_p,
output [0:0] HSMC_GXB_TX_p,
output HSMC_SDI_Rate_Sel_1,
output HSMC_SDI_Rate_Sel_2,
output HSMC_EQBypass_1,
output HSMC_EQBypass_2,
output HSMC_SDI_CLK_Sel,
output HSMC_SDI_XTAL_Sel,
///////// I2C /////////
output I2C_SCL,
inout I2C_SDA,
///////// KEY /////////
input [3:0] KEY,
///////// LEDG /////////
output [7:0] LEDG,
///////// LEDR /////////
output [9:0] LEDR,
///////// SD /////////
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT,
///////// SRAM /////////
output [17:0] SRAM_A,
output SRAM_CE_n,
inout [15:0] SRAM_D,
output SRAM_LB_n,
output SRAM_OE_n,
output SRAM_UB_n,
output SRAM_WE_n,
///////// SW /////////
input [9:0] SW,
///////// UART /////////
input UART_RX,
output UART_TX
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire reset_hsmc_xcvr_phy;
wire reset_xcvr_reconfig;
wire [19:0] SDI_Databus20;
wire TRS_First_Word;
wire TRS_Locked = 1'b1;
wire [10:0] Line_Number;
wire CLOCK_148_5MHZ;
wire CLOCK_74_25MHZ;
wire reset1_n;
wire reset2_n;
wire reset_n;
//-----HSMC Daughter Card support
reg SDI_Rate_Sel_1 = 1'b0;
reg SDI_Rate_Sel_2 = 1'b0;
reg EQBypass_1 = 1'b0;
reg EQBypass_2 = 1'b0;
reg SDI_CLK_Sel = 1'b0;
reg SDI_XTAL_Sel = 1'b0;
///////////////////////////////////////
//=======================================================
// assignments
//=======================================================
assign HSMC_EQBypass_1 = EQBypass_1; // RX Cable Equalizer. High = Bypass, Low = Use equalizer.
assign HSMC_EQBypass_2 = EQBypass_2; // RX Cable Equalizer. High = Bypass, Low = Use equalizer.
assign HSMC_SDI_Rate_Sel_1 = SDI_Rate_Sel_1; // TX Cable Driver. High = SD, Low = HD/3G
assign HSMC_SDI_Rate_Sel_2 = SDI_Rate_Sel_2; // TX Cable Driver. High = SD, Low = HD/3G
assign HSMC_SDI_CLK_Sel = SDI_CLK_Sel;
assign HSMC_SDI_XTAL_Sel = SDI_XTAL_Sel;
//=======================================================
// REG/WIRE declarations
//=======================================================
PLL_XCVR XCVR_PLL_1 (
.refclk(CLOCK_50_B7A), // refclk.clk
.rst(~CPU_RESET_n), // reset.reset
.outclk_0(CLOCK_148_5MHZ), // outclk0.clk
.outclk_1(CLOCK_74_25MHZ), // outclk1.clk
.locked(reset_n) // locked.export
);
//---Generated SDI v16.1 IP CORE. Bidirectional. No Protocol block (Transceiver Only).
SDI_v16_t SDI_v16_Bidirectional1 (
.rst_rx ( ~reset_n ),
.rst_tx ( ~reset_n ),
.rx_serial_refclk ( CLOCK_74_25MHZ ), // input must be nominally 1/20th of the serial data rate. This clock trains the internal PLL.
.tx_pclk ( CLOCK_74_25MHZ ),
.tx_serial_refclk ( CLOCK_74_25MHZ ),
.sdi_rx ( HSMC_GXB_RX_p ), // Pin#
.txdata ( SDI_Databus20 ), // input [19:0] 20bits to HD-SDI
.refclk_rate ( 1'b1 ), // Set input to 1 for 148.5-MHz RX serial reference clock, to 0 for a 148.35-MHz receiver serial reference clock.
.rx_protocol_locked ( TRS_Locked ), // input
.rx_xcvr_trs_lock ( TRS_Locked ), // input stays high when valid TRS packets are detected.
.sdi_reconfig_togxb ( ),
.sdi_tx ( HSMC_GXB_TX_p ), // Pin#
.rxdata ( SDI_Databus20 ), // output [19:0] 20bits from HD-SDI
.rx_data_valid_out ( ),
.rx_clk ( CLOCK_74_25MHZ ), // input
.rx_status ( ),
.tx_status ( ),
.detected_rate ( ),
.gxb_tx_clkout ( ),
.sdi_reconfig_fromgxb ( )
);
endmodule
