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Altera_Forum's avatar
Altera_Forum
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18 years ago

Cyclone III Development board errata

Hello everyone,

I've designed a new system from scratch on the cyclone iii development board (http://www.altera.com/products/devkits/altera/kit-cyc3.html) and I found a few errors in the files provided by Altera. I don't think I've seen them before on the forum, so I thought I would share them with you, so that you don't loose as much time as me to find them out ;)

SRAM pins

4 pin assignments on the flash/sram data bus are wrong, on the "cycloneIII_3c120_dev_my_first_fpga", "cycloneIII_3c120_dev_niosII_standard" and "cycloneIII_3c120_dev_quartus_pinouts" design examples. 2 of these pins are connected to ground, which makes it somewhat difficult to write what you want in the SRAM. Only the upper word is concerned, so the flash (that only uses the lower word) is not affected. You must change the following assignments:

fsd PIN_C8 -> PIN_B8
fsd PIN_D9 -> PIN_C8
fsd PIN_F11 -> PIN_D9
fsd PIN_F10 -> PIN_E7

The second error is in the reference manual, page 2-39. It says that the chip select pins for both the character and the graphical LCDs are connected to pin AB24. The chip enable for the text LCD is in fact connected to pin AC24. The example designs are correct though.

On a personal note I found the name they gave the LCD pins very confusing, because it is impossible to tell which signals are common to the two LCD displays, and which are specific to one of them. I renamed the signals to something like lcd_txt_*, lcd_gr_* and kept only the names lcd_* for common signals.

Is there a way to tell this to Altera so that they can correct all this for the next version?

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Ciao Daixiwen

    first of all thanks for fast reply. Sorry if I reported this post in the wrong position, I'll update position.

    Could someone explain to me how this post could be moved from current position to Altera development board..
  • Altera_Forum's avatar
    Altera_Forum
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    You can see in the schematic that LCD_CONT is only connected to the LCD module and the voltage divider. It has no direct or indirect connection to a FPGA pin. So it won't appear in FPGA pin list or *.qsf file. To make the contrast programmable, you would e.g. connect three resistors in a binary graduation (1:2:4 R) between the voltage divider tap and FPGA outputs. But I don't see the purpose for an evaluation board, may be for a retail product.

  • Altera_Forum's avatar
    Altera_Forum
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    good explanation FvM

    I've 2 dark points:

    Usually my lcd is very low contrasted and only by looking with particular angle I can see display contents, but ss soon as I re-boot my board very close to finilize LCD I can see a very good image on display... why?

    On my board DE0 I have the follwoing Physical pinout:

    GND

    VCC

    CONT

    RS

    RW

    EN

    D0

    ..

    D7

    BL

    GND

    my second question is how can I root connection CONT, I have a hole on board but I can't understand how can I write on this pin-out.

    Could you please help me, or drive on the right root ?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    Which LCD module are you using? As far as I know, there's no module shipped with DE0. If you are using a different LCD module than that planned by Terasic, you should check the contrast voltage requirements. It may be necessary to change the voltage divider R11/R14.

    As said, the LCD contrast voltage isn't programmable with DE0. In so far, there's no option to change it in software.

    You have been talking about low contrast. That's a different thing than switched off back light. I presume that you are able to see the difference.
  • Altera_Forum's avatar
    Altera_Forum
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    FvM not I've catched your point no possibilities to control the contrast from FPGA. I have the LCD pin for contrast linked to the board and I can't see a good contrast. Maybe an open circuit could be better!?!?!