Cyclone III development board and USB FT245BL

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Is the protocol to program Altera ICs (via JTAG) protected?

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No. And it is well documented.

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I would imagine that the IP in Altera's Cyclone II Kit (MAX 3000 CPLD - EPM3128AT) or the standalone USB Blaster (EPM7064), could be re-written based on the (published?) protocol, no?

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Yes, you could do that. But then it won't work anymore with Altera tools.

The Altera tools (Programmer, Signal Tap II, etc) all depend on a specific USB Blaster protocol. Is this protocol that it is undisclosed. Otherwise you could make your own Max II IP compatible with the USB Blaster protocol.

And also the jtagserver protocol is undisclosed. If the latter was published, you could replace Altera's jtagserver with your own.

To access Altera FPGA and CPLD through JTAG, yo have basically two options:

- Use third party JTAG tools. All production related actions (programming of CPLD, test by boundary scan can be done by industry standard protocols and are basically documented. Development related actions, e. g. download of temporary JTAG configurations from *.sof files is using proprietary JTAG instructions, but documented as well. The Virtual JTAG protocol involved with most communication between tools and FPGA has been recently documented in virtual JTAG MegaFunction manual, the specific application protocols, e. g. for SignalTap II or In-System Memory Editor are undisclosed, but more or less simple.

- Use Altera JTAG programming hardware through Altera software stack. Only part of the existing interfaces respectively access pathes has been yet documented, particularly access of virtual JTAG through tcl commands and a JTAG UART interface.

If you understand the USB Blaster protocol, you can also combine both methods, perform generic JTAG through USB Blaster. It may be interesting for accessing other vendors devices in the JTAG chain or boundary scan tests of Altera devices through an existing USB Blaster.

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If you understand the USB Blaster protocol, you can also combine both methods, perform generic JTAG through USB Blaster. It may be interesting for accessing other vendors devices in the JTAG chain or boundary scan tests of Altera devices through an existing USB Blaster.

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That would definitely be my goal.. have the Altera FPGA support the ByteBlaster protocol so that any JTAG devices that hang off of it may be programmed via the Quartus software. I use Quartus/USB-Blaster in Windows, but isn't there an (open-source) Linux version?

Doing some poking around, it seems the USB Protocol was once posted, but has since been taken down

(

http://wiki.openchip.org/index.php/altera_usb_blaster

http://wiki.openchip.org/index.php/altera_bitblaster

)

On the bright side, there appears to be one project that might have already done this before, or at least come to close..

http://www.ixo.de/info/usb_jtag/

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We pointed several solutions for accessing the USB connector.

The easiest is by far using TCL scripts, but then it is probably the slowest.

A second choice would be to use the unofficially documented (seems more like not officially supported, rather than undocumented) jtag-uart interface using the atlantic DLL. Or you can use one of the undocumented interfaces, including direct access to the USB-Blaster using FTDI DLL API.

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After reading the topic I am still not sure what's the best way to get FTDI USB to work. Did anybody really try to use FTDI D2XX DLL API for USB to PC communication?

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After reading the topic I am still not sure what's the best way to get FTDI USB to work. Did anybody really try to use FTDI D2XX DLL API for USB to PC communication?

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Well, after all I just took external USB DLP-USB1232H and connected to HSMC. Works good with ~ 80 Mbps throughput.

>>"I just took external USB DLP-USB1232H and connected to HSMC".

- How did you do that? I need to do the same, can you please elaborate? My design has a DVI board on the HSMC, is there something I can buy to share that HSMC with the DVI? found5520@yahoo.com

Thanks.

hi everybody

i recently begin programing uc/os for nios II board, when i run its examples,they run without error, but when i write a new program myself it gets errors for include"includes.h" and for stack functions like os_stk task1[task1_stacksize] and many other functions, so i want to know should change any setting or add any libraries when i begin a new project?

thank you

Sepideh

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>>"I just took external USB DLP-USB1232H and connected to HSMC".

- How did you do that? I need to do the same, can you please elaborate? My design has a DVI board on the HSMC, is there something I can buy to share that HSMC with the DVI? found5520@yahoo.com

Thanks.

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Well, I just took that USB module and connected it to HSMC (through HSMC debug header). I assigned appropriately input, output, inout pins on FPGA with those on USB. Potential issue here is voltage levels on both sides. USB has 3.3V pins and FPGA 2.5V. USB recognizes 2.5V inputs, so that's fine. 3.3V inputs to FPGA also is fine, I just turned off clamping diodes on FPGA inputs to protect them. I am not sure about DVI, you need to understand voltage/current levels to not to burn pins on chips