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Altera_Forum
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17 years ago

Cyclone II DSP Develpment Kit . Analysis & Synthesis Error

Hello,

I'm using Altera DSP Develpment Kit, Cyclone II Edition.

Reference Design Number: AN427.

I do Analysis & Synthesis very well at Quartus II 6.0.

But, when I change the following parameters in Scaler V1.0.0 IP:

-- Select: Enable image clipping.

-- Width 100, X offset 10.

-- Height 100, Y offset 10.

and do generate at Matlab 7.1.

Then, return to Quartus II 6.0, there are errors while Analysis & Synthesis.

The error message are:

Error: Port "spaceavail_en" does not exist in macrofunction "fu_msgs_read_to_write_main"

.. and other more 7 errors just like that.

Please give me instruction to solve these problems.

Thanks!

Kevin Ding

2008.0924.Wed

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Try to upgrade Quartus II to the latest release. You can download it freely from the Altera website.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    The higher version could not let the lab reference project loaded well.

    The IP is not licensed, but I just wanna evaluation before purchase license.

    When I click the Error Msg

    (port "dataavail_en" does not exist in macrofunction "fu_msgs_read_to_write_main")

    it indicates to file my_tbb.vhd, hilight to:

    fu_msgs_read_to_write_main : ALT_FIFO

    GENERIC MAP (NAME=>"fu_msgs_read_to_write_main", WIDTH=>2, DEPTH=>2, ADDRESS_WIDTH=>1, FAMILY=>FAMILY, SIMULATION=>SIMULATION, MANUFACTURER=>MANUFACTURER, OPTIMIZED=>OPTIMIZED)

    PORT MAP (clock=>clock, reset=>reset_int, ena_read=>ena_thread_0, ena_write=>ena_thread_1, stall_write=>S_fu_msgs_read_to_write_main_stall_write, stall_read=>S_fu_msgs_read_to_write_main_stall_read, writenext_en=>fu_msgs_read_to_write_main_writenext_en, readnext_en=>fu_msgs_read_to_write_main_readnext_en,

    wdata=>fu_msgs_read_to_write_main_wdata, writenext=>fu_msgs_read_to_write_main_writenext, readnext=>fu_msgs_read_to_write_main_readnext, rdata=>fu_msgs_read_to_write_main_rdata, dataavail=>fu_msgs_read_to_write_main_dataavail);