Cyclone II DSP Develpment Kit . Analysis & Synthesis Error

The higher version could not let the lab reference project loaded well.

The IP is not licensed, but I just wanna evaluation before purchase license.

When I click the Error Msg

(port "dataavail_en" does not exist in macrofunction "fu_msgs_read_to_write_main")

it indicates to file my_tbb.vhd, hilight to:

fu_msgs_read_to_write_main : ALT_FIFO

GENERIC MAP (NAME=>"fu_msgs_read_to_write_main", WIDTH=>2, DEPTH=>2, ADDRESS_WIDTH=>1, FAMILY=>FAMILY, SIMULATION=>SIMULATION, MANUFACTURER=>MANUFACTURER, OPTIMIZED=>OPTIMIZED)

PORT MAP (clock=>clock, reset=>reset_int, ena_read=>ena_thread_0, ena_write=>ena_thread_1, stall_write=>S_fu_msgs_read_to_write_main_stall_write, stall_read=>S_fu_msgs_read_to_write_main_stall_read, writenext_en=>fu_msgs_read_to_write_main_writenext_en, readnext_en=>fu_msgs_read_to_write_main_readnext_en,

wdata=>fu_msgs_read_to_write_main_wdata, writenext=>fu_msgs_read_to_write_main_writenext, readnext=>fu_msgs_read_to_write_main_readnext, rdata=>fu_msgs_read_to_write_main_rdata, dataavail=>fu_msgs_read_to_write_main_dataavail);