Critical Warning: DDR Timing requirements not met

I have built a FPGA design with NIOS. But there are some timing warnings as below:

Critical Warning: DDR Timing requirements not met

Overwriting existing clock: <Clock Name>

When I was debugging the same on stp . I could see read_request and address is being sent correctly by the custom RTL IP. But I am not able to receive i_ddr_data_valid signal from ddr. Data seems to correct on i_ddr_read_data of DDR.

How should I go about solving this issue?