Forum Discussion
Yogesh
Occasional Contributor
Occasional ContributorCritical Warning: DDR Timing requirements not met
I have built a FPGA design with NIOS. But there are some timing warnings as below:
Critical Warning: DDR Timing requirements not met
Overwriting existing clock: <Clock Name>
When I was debugging the same on stp . I could see read_request and address is being sent correctly by the custom RTL IP. But I am not able to receive i_ddr_data_valid signal from ddr. Data seems to correct on i_ddr_read_data of DDR.
How should I go about solving this issue?
3 Replies
yoichiK_alteraContributor
Hi
Since you are receiving the DDT timing critical warning do you see the timing violation in Timing Analysis report ?
YogeshYes , There are about 12 paths violated inside SDRAM.
- yoichiK_altera
then why can not you close the timing ?
